PIC18F6585/8585/6680/8680
DS30491C-page 164
2004 Microchip Technology Inc.
14.0
TIMER3 MODULE
The Timer3 module timer/counter has the following
features:
16-bit timer/counter
(two 8-bit registers; TMR3H and TMR3L)
Readable and writable (both registers)
Internal or external clock select
Interrupt on overflow from FFFFh to 0000h
Reset from CCP module trigger
Figure 14-1 is a simplified block diagram of the Timer3
module.
Register 14-1 shows the Timer3 Control register. This
register controls the operating mode of the Timer3
module and sets the Enhanced CCP1 and CCP2 clock
source.
Register 12-1 shows the Timer1 Control register. This
register controls the operating mode of the Timer1
module, as well as containing the Timer1 oscillator
enable bit (T1OSCEN) which can be a clock source for
Timer3.
REGISTER 14-1:
T3CON: TIMER3 CONTROL REGISTER
R/W-0
RD16
T3CCP2
T3CKPS1
T3CKPS0
T3CCP1
T3SYNC
TMR3CS
TMR3ON
bit 7
bit 0
bit 7
RD16: 16-bit Read/Write Mode Enable bit
1
= Enables register read/write of Timer3 in one 16-bit operation
0
= Enables register read/write of Timer3 in two 8-bit operations
bit 6, 3
T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits
1x
= Timer3 is the clock source for compare/capture of CCP1 and CCP2 modules
01
= Timer3 is the clock source for compare/capture of CCP2 module,
Timer1 is the clock source for compare/capture of CCP1 module
00
= Timer1 is the clock source for compare/capture of CCP1 and CCP2 modules
bit 5-4
T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits
11
= 1:8 prescale value
10
= 1:4 prescale value
01
= 1:2 prescale value
00
= 1:1 prescale value
bit 2
T3SYNC: Timer3 External Clock Input Synchronization Control bit
(Not usable if the system clock comes from Timer1/Timer3.)
When TMR3CS = 1:
1
= Do not synchronize external clock input
0
= Synchronize external clock input
When TMR3CS = 0:
This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.
bit 1
TMR3CS: Timer3 Clock Source Select bit
1
= External clock input from Timer1 oscillator or T13CKI
(on the rising edge after the first falling edge)
0
= Internal clock (FOSC/4)
bit 0
TMR3ON: Timer3 On bit
1
= Enables Timer3
0
= Stops Timer3
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
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